With the advancement of electronic technology, modern military equipment has entered the era of information and electronics. The complexity and variety of such equipment necessitate robust maintenance systems. A widely adopted framework is the three-level maintenance system, as outlined below:
| Maintenance Level | Fault Isolation Target | Primary Objective |
|---|---|---|
| Organizational / Field Level | Line Replaceable Unit (LRU) | Rapid restoration of operational capability. |
| Intermediate Level | Shop Replaceable Unit (SRU) / Module | Detailed repair and module testing. |
| Depot Level | Component Level | Overhaul and repair of individual components. |
The field level is particularly critical for military UAV operations, where rapid turnaround is essential. This level requires test equipment that is portable, fast-operating, and capable of isolating faults to an LRU. The device described herein is a handheld field checker designed specifically for the frontline testing and verification of Identification Friend or Foe (IFF)/Secondary Surveillance Radar (SSR) transponders onboard military UAVs.
Overall System Design and Technical Features
Equipment Composition
The field checker employs a highly integrated, handheld design. It incorporates the power supply, RF transceiver module, signal processing board, display, keypad, and necessary avionics or RF connectors within a single compact enclosure. The system block diagram is as follows:
Block Diagram: External Power → Power Module → Internal DC Rails. User Input via Keypad → Signal Processing Board (DSP/FPGA) → Control for RF Transceiver & Display Output. RF Transceiver ↔ Antenna Port. Signal Processing Board ↔ OLED Display.
Key Technical Characteristics
The design philosophy centers on modularity and high-density integration. Internally, ultra-miniature connectors link the transceiver, power, and processing modules, enhancing reliability while minimizing size and cost. Key features include:
- Rugged Display: Utilizes a dot-matrix OLED display operational from -40°C to +55°C.
- Intuitive Interface: Features a user-friendly menu and result display for efficient operation.
- Rapid Deployment: Incorporates a quick-detach antenna for fast setup and teardown.
- Military-Grade Robustness: Designed to meet stringent environmental requirements for military UAV ground support equipment.
Operational Principle
The checker operates on the secondary surveillance radar principle, using an interrogate-response protocol. It emits coded RF interrogation pulses. The Unit Under Test (UUT)—the military UAV transponder—receives and decodes these pulses. If the decoding is correct, the transponder replies with the appropriate RF pulse train. The checker analyzes the received reply for correctness and timing to determine the UUT’s health status.
Pre-Test Procedures
Military UAV avionics often have security protocols requiring volatile memory for critical software. Upon power-up, the operational software and mission data (e.g., crypto keys) must be loaded. Therefore, functional testing is preceded by a data injection phase.
- Data Injection: The checker connects to the UUT via a CAN bus interface. The operator selects the required software and crypto data files, which are transmitted to the transponder. This process also verifies the integrity of the data interface.
- Operational Mode Setting: Configuration commands (e.g., mode settings, code assignments) are sent to the UUT via the same CAN bus to prepare it for testing.
Functional Testing Sequence
Before testing the UUT, the checker performs a power-on self-test to verify its own functionality.
| Test Mode | Interrogation Type | Checker Action | Pass Criteria |
|---|---|---|---|
| ATC Function Check | Mode A (Identity) & Mode C (Altitude) | Transmits A- and C-mode interrogs. Measures Reply Efficiency (RE). | RE exceeds a predefined threshold (e.g., >90%). |
| Selective Identification Feature (SIF) Check | Mode S or Military Modes | Transmits interrogations with specific address/codes. Checks for correct code reply. | Correct code received with high RE. |
If the UUT fails a test, frontline maintenance action involves replacing either the signal processing board or the transceiver module (LRUs) to isolate the fault, consistent with field-level maintenance objectives.
Detailed Circuit Design
Signal Processing Board
This board is the computational core. It integrates control, encoding/decoding, local code generation, crypto functions, clock management, self-test interfaces, A/D conversion, digital down-conversion, and data loading capabilities.
Circuit Flow: The transceiver module outputs two signals: an analog ATC video pulse and an Intermediate Frequency (IF) signal for specific military identification modes.
- A/D Conversion: The IF signal is sampled by a dual-channel, low-power 14-bit ADC (e.g., LTC2299). Its power is separately regulated by a dedicated LDO (e.g., TPS70302) for noise isolation.
- Digital Signal Processing (FPGA): The digitized IF signal undergoes Digital Down-Conversion (DDC) within the FPGA. The process can be summarized by the equations for a quadrature mixer:
$$ I[n] = S[n] \cdot \cos(2\pi f_{LO} n T_s) $$
$$ Q[n] = S[n] \cdot \sin(2\pi f_{LO} n T_s) $$
where \(S[n]\) is the sampled IF signal, \(f_{LO}\) is the digital Local Oscillator frequency, and \(T_s\) is the sampling period. The resulting I/Q baseband data is then filtered, demodulated (e.g., despread, decoded). - Data Analysis (DSP): The processed data is sent to a Digital Signal Processor. The DSP executes higher-level algorithms for pulse detection, code validation, and statistical analysis (e.g., calculating Reply Efficiency). The final results are formatted and sent to the OLED display.
RF Transceiver Module
This module handles all RF generation, transmission, and reception.
Transmit Path: A frequency synthesizer (e.g., SWM501K) generates the RF carrier and Local Oscillator (LO) signals, locked to a stable 20MHz reference. The RF signal is gated/modulated to form the interrogation pulses, which pass through an antenna switch to be radiated.
Receive Path:
- The LO signal is amplified and split. One path is for monitoring; the other is fed to the receiver mixer.
- Replies from the UUT are received by the antenna, filtered, and amplified.
- In the mixer, the received RF signal is down-converted using the LO to a lower IF (e.g., 60MHz). This is expressed as:
$$ f_{IF} = |f_{RF} – f_{LO}| $$ - The IF signal is filtered and sent to the processing board’s ADC.
- For ATC video, a separate detector circuit extracts the pulse envelope, producing a video signal sent directly to the FPGA for timing analysis.
Mechanical and Structural Design
To meet field requirements for shock, vibration, environmental sealing (IP rating), and Electromagnetic Compatibility (EMC), the mechanical design is critical. The main chassis is machined from a single block of aluminum alloy, providing excellent structural integrity, heat sinking (via finned sections near the power components), and inherent EMI shielding. A rear aluminum cover is secured with countersunk screws, ensuring a smooth exterior and robust seal. This compact and rugged form factor is essential for deployment in harsh environments supporting military UAV operations.
Software Architecture
The embedded software is partitioned between the FPGA and the DSP, optimizing performance.
FPGA Program
The FPGA implements time-critical, hardware-centric functions. Its overall architecture is managed by a top-level control module.
Core FPGA Functions Include:
- Digital Down-Converter (DDC): Implements the quadrature mixing and filtering as per the equations above.
- Pulse Detection & Measurement: Identifies pulses in the ATC video and digital data streams, measuring pulse width (PW) and time of arrival (TOA). Detection often uses a threshold comparison:
$$ \text{Detection} = \begin{cases} 1 & \text{if } V_{signal}[n] > V_{threshold} \\ 0 & \text{otherwise} \end{cases} $$ - Interface Management: Controls the ADC, communicates with the DSP via parallel bus or SPI, and manages the keypad scan logic.
- Timing Generation: Produces precise timing for interrogation pulse generation and system synchronization.
DSP Program
The DSP handles complex control logic, data analysis, and the user interface.
Main DSP Tasks:
- System Control & Sequencing: Manages the overall test workflow (self-test, data injection, ATC/SIF tests).
- Data Processing: Receives raw detection data from the FPGA. Decodes reply codes, validates them against the interrogation, and calculates performance metrics like Reply Efficiency:
$$ RE = \frac{\text{Number of Valid Replies}}{\text{Number of Interrogations Sent}} \times 100\% $$ - User Interface (UI) Management: Drives the OLED display, renders menus, and interprets keypad inputs.
- Communication Protocols: Implements the CAN bus protocol for data injection and configuration of the UUT.
This synergistic design between FPGA and DSP ensures real-time signal processing capability coupled with flexible high-level control, making the portable field checker a powerful and reliable tool for maintaining the critical transponder systems on modern military UAVs.