In the rapidly evolving landscape of unmanned aerial vehicles, the integration of increasingly complex payload modules has become a defining trend. These sophisticated systems, encompassing high-resolution cameras, LiDAR, communication relays, and electronic warfare suites, demand a stable and predictable operating environment to guarantee both mission success and airframe safety. The vibration environment on a UAV drone, generated by rotating machinery, aerodynamic forces, and propulsion systems, poses a significant threat to the reliability of these sensitive payloads. Traditional onboard data acquisition systems have addressed this challenge through local storage, recording raw sensor data onto high-capacity memory modules that are only retrieved and analyzed post-flight. This paradigm, while providing a complete dataset for offline forensic analysis, is inherently incapable of supporting real-time decision-making during flight. The ground control station remains blind to the instantaneous vibration status of the mission payload, potentially missing early signs of mechanical degradation, resonance buildup, or incipient failure. Moreover, streaming the full raw data stream over the limited-bandwidth air-ground link would consume resources that are critically needed for flight control telemetry, thus degrading the overall operational envelope of the UAV drone.
To overcome this bottleneck, we developed a dedicated FPGA-based real-time monitoring system that performs on-board signal processing to extract key vibration parameters before transmission. By implementing a Finite Impulse Response (FIR) low-pass filter and a Fast Fourier Transform (FFT) core directly in hardware, the system reduces the data rate from several kilobytes per second to a few hundred bytes per second, while preserving the essential frequency-domain information required for condition monitoring. This design allows the ground control station to continuously assess the vibration state of the mission payload with minimal impact on the communication channel. In parallel, the system retains a local SD card recorder that stores the complete raw time-domain data for post-flight analysis, ensuring that no information is lost for deeper investigation.
System Architecture and Hardware Design
The core of the monitoring system is an Artix-7 series FPGA, selected for its balance of logic density, low power consumption, and the availability of hardened DSP slices and block RAM that are essential for real-time digital signal processing. The system integrates three major functional blocks: a multi-channel analog front-end with a high-precision ADC, a digital processing pipeline that includes the FIR filter and FFT engine, and a communication interface that packages the extracted parameters into a compact frame format for transmission over an RS-422 link. A detailed breakdown of the hardware components is given in the table below.
| Component | Model / Specification | Function |
|---|---|---|
| Vibration sensor | 3273M2 tri-axial accelerometer | Measures X, Y, Z vibration up to ±20 g |
| Analog multiplexer | MAX4638 | Selects one of three sensor channels for ADC |
| Analog-to-digital converter | AD7880 (12-bit, up to 66 kSPS) | Digitizes analog vibration signal |
| FPGA | Artix-7 XC7A35T | System control, FIR filter, FFT, data packing |
| Serial transceiver | MAX3490 (RS-422) | Differential transmission up to 10 Mbps |
| Data storage | MicroSD card (FAT32) | Raw data logging for post-flight analysis |
| Power regulators | TPS7A49, TPS54332, TPS82130 | Generate 24 V, 12 V, 3.3 V, 1.8 V, 1.0 V |
The analog front-end uses the MAX4638 multiplexer to sequentially connect the three output channels of the 3273M2 accelerometer to the AD7880 ADC. The sampling rate per channel is set to 5 kHz, which satisfies the Nyquist criterion for the target vibration range of 5–100 Hz (low-frequency) and also provides adequate oversampling for the higher-frequency content up to 2 kHz that is stored locally but not processed in real time. The ADC operates in a continuous conversion mode, and the FPGA reads the 12-bit data via a parallel interface. To maintain signal integrity, the analog inputs are buffered and decoupled with passive RC filters (cutoff ≈ 10 kHz) to suppress high-frequency noise before digitization.
The digital processing pipeline begins by buffering the incoming ADC samples into a FIFO. The FIFO depth is set to 512 samples per channel, which is sufficient to decouple the ADC’s asynchronous conversion rate (5 kHz clock domain) from the main FPGA processing clock (50 MHz). The data from the FIFO is then fed into the FIR filter block for decimation and low-pass filtering. After filtering, the signal is downsampled to 200 Hz, and blocks of 256 samples are accumulated before being passed to the FFT engine.
Digital Signal Processing on FPGA
FIR Low-Pass Filter Implementation
The primary objective of the FIR filter is to remove high-frequency components (above 100 Hz) that are not of interest for the low-frequency vibration monitoring of the UAV drone’s mechanical structure. Additionally, the filter serves as an anti-aliasing stage before decimation, preventing frequency folding when the sample rate is reduced from 5 kHz to 200 Hz. We designed a 16-tap equiripple FIR filter using the FDA Tool, with a passband edge at 100 Hz and a stopband attenuation of 60 dB. The coefficients were quantized to 12-bit signed integers to match the ADC resolution and to simplify the multiply-accumulate operations. Because the FPGA contains dedicated DSP48E1 slices, each MAC operation can be completed in a single clock cycle at 50 MHz. However, to conserve resources, we adopted a serial architecture where a single multiplier is time-multiplexed across all 16 taps. The serial structure is illustrated conceptually by the difference equation governing the filter output:
$$ y[n] = \sum_{k=0}^{15} h[k] \cdot x[n-k] $$
where $$h[k]$$ are the fixed coefficients and $$x[n]$$ is the input sample sequence. The filter is realized using a shift register of length 16, a coefficient ROM, a single multiplier, and an accumulator. A state machine controls the addressing: at each 6.25 MHz clock enable (derived from the 50 MHz system clock by a divide-by-8 counter), the shift register contents are multiplied by the corresponding coefficient and accumulated. After 16 cycles, the accumulated result is output as the filtered sample, and the accumulator is reset for the next sample. The measured frequency response of the implemented filter shows a passband ripple less than 0.5 dB and a stopband attenuation exceeding 55 dB, meeting the design requirements.
| Parameter | Value |
|---|---|
| Filter type | Equiripple low-pass |
| Number of taps | 16 |
| Passband edge | 100 Hz |
| Stopband edge | 150 Hz |
| Stopband attenuation | 60 dB |
| Input/output bit width | 12-bit signed |
| Quantization | 12-bit fractional (Q1.11 format) |
| Implementation style | Serial (single MAC) |
| Sample rate (input) | 5 kHz |
| Sample rate (output) | 200 Hz (decimated by 25) |
We validated the filter behavior using ModelSim simulation. A test signal composed of a 50 Hz sine wave and a 500 Hz sine wave was fed into the filter. The output waveform confirmed that the 500 Hz component was attenuated by more than 50 dB, while the 50 Hz component passed with minimal distortion. This verification ensures that only the low-frequency vibrations relevant to engine and rotor dynamics are retained for further spectral analysis.
FFT Core Hardware Implementation
The filtered and decimated signal, now at 200 Hz, contains frequency components only up to 100 Hz (the filter stopband). To perform spectral analysis, we apply a 256-point radix-2 decimation-in-time FFT. The choice of N=256 yields a frequency resolution of $$ \Delta f = \frac{f_s}{N} = \frac{200}{256} \approx 0.78 \text{ Hz}$$, which is sufficient to distinguish closely spaced vibration peaks (e.g., blade passage frequencies) that may differ by only 1 Hz. Since the input sequence length after filtering is continuous, we buffer 256 consecutive filtered samples before initiating the FFT. If fewer than 256 samples are available during system initialization, the remaining positions are padded with zeros.
The FFT engine is designed using a pipelined architecture with eight stages (since $$ \log_2(256)=8 $$). Each stage implements a single radix-2 butterfly operation, illustrated by the well-known formula:
$$ X_{m+1}[k] = X_m[k] + W_N^k \cdot X_m[k+N/2] $$
$$ X_{m+1}[k+N/2] = X_m[k] – W_N^k \cdot X_m[k+N/2] $$
where $$W_N^k = e^{-j2\pi k/N}$$ is the twiddle factor, and $$X_m$$ are the complex data at stage m. The twiddle factors are precomputed and stored in a ROM with 128 entries (since symmetry reduces storage). To optimize resource usage, we reuse a single butterfly unit across all stages and process data in a serial manner: at each clock cycle, one butterfly pair is computed using DSP slices for the complex multiplication and addition. The intermediate results are written back to a dual-port block RAM that holds the 256 complex numbers. After eight stages, the output is in bit-reversed order, which is then reordered to natural order using a simple counter-based address generator.
| Resource | Used | Available | Utilization (%) |
|---|---|---|---|
| Slice LUTs | 1,245 | 20,800 | 5.98 |
| Slice registers | 1,872 | 41,600 | 4.50 |
| DSP48E1 slices | 4 | 90 | 4.44 |
| Block RAM (36 kb each) | 6 | 50 | 12.0 |
After the FFT computation, the complex spectrum is converted to magnitude using the approximation: $$ |X[k]| \approx \max(\text{Re}, \text{Im}) + 0.375 \cdot \min(\text{Re}, \text{Im}) $$, which avoids the use of a square root unit and is accurate to within 2% for the targeted SNR. The resulting magnitude spectrum for each of the three axes is then packed into a custom frame format. Each frame contains a 2-byte sync header (0xEE repeated four times), followed by 192 bytes of payload (64 bytes per axis, representing the 256-point magnitude data in 16-bit integer format but only the first 128 bins are transmitted since the spectrum is symmetric and the last 128 are redundant), and terminated by a 4-byte sync trailer (0xFF repeated four times). The frame is clocked out at 115,200 baud over the RS-422 link, well within the available bandwidth of a typical UAV drone telemetry channel.
Power Management Considerations
The system is powered from the UAV drone’s on-board 28 V DC bus, which is typical for military and industrial drones. A multi-stage regulation scheme ensures clean and stable voltages for all components while minimizing heat dissipation. The first stage uses a TPS7A49 low-dropout regulator to generate 24 V with 1% accuracy for the accelerometer, which requires a stable excitation voltage to maintain sensitivity. The second stage employs a TPS54332 switching regulator to step down 28 V to 12 V with an efficiency above 90%. This 12 V rail then feeds three TPS82130 integrated DC-DC modules to produce 3.3 V (for the ADC, RS-422 transceiver, and SD card), 1.8 V (for FPGA I/O banks), and 1.0 V (for FPGA core logic). Each regulator is accompanied by appropriate input/output capacitors and ferrite beads to suppress switching noise. The power tree is summarized in the following table.
| Voltage Rail | Source | Load(s) | Max Current |
|---|---|---|---|
| 24 V | TPS7A49 (from 28 V) | 3273M2 accelerometer | 50 mA |
| 12 V | TPS54332 (from 28 V) | Intermediate rail for three TPS82130 | 500 mA |
| 3.3 V | TPS82130 #1 | AD7880, MAX3490, MAX4638, SD card | 200 mA |
| 1.8 V | TPS82130 #2 | FPGA VCCIO (bank 0,1,2) | 150 mA |
| 1.0 V | TPS82130 #3 | FPGA VCCINT | 1.2 A |
Experimental Validation
To verify the complete system, we conducted a controlled vibration test using an R0500SL electrodynamic shaker. The tri-axial accelerometer was rigidly mounted on the shaker table, and the system was configured to acquire data for approximately 200 ms. The shaker was programmed to produce a composite vibration signal consisting of four low-frequency tones (91, 92, 93, and 94 Hz) at amplitudes within the ±20 g range, plus a 500 Hz tone to simulate high-frequency disturbance. The real-time monitoring output was captured by a host PC connected to the RS-422 port via a USB-to-Serial adapter. The received data frames were decoded and the magnitude spectra were plotted.
The post-experiment analysis of the locally stored raw data confirmed the correct operation of the system. The plots revealed four distinct spectral peaks at the expected frequencies (91–94 Hz), while the 500 Hz component was completely absent, demonstrating the effectiveness of the FIR anti-aliasing filter. The frequency resolution was measured to be approximately 0.78 Hz, consistent with the 256-point FFT at 200 Hz sampling rate. The system successfully transmitted the parameterized spectral data over the low-bandwidth link, occupying only 0.1152 kbps per axis, which is a reduction of more than 99% compared to transmitting raw 5 kHz 12-bit data (which would require 60 kbps per axis). This experiment proves that the design meets the real-time monitoring requirements for UAV drone mission payload operating environments without overwhelming the telemetry link.
Comparative Analysis of Feature Extraction Algorithms
While the FIR-FFT hardware approach is effective for periodic spectral monitoring, we also evaluated alternative feature extraction strategies to assess their suitability for future upgrades. For instance, on-board diagnostics could benefit from time-domain statistical features such as root mean square (RMS), crest factor, and kurtosis, which can be computed with minimal hardware overhead using accumulator and comparator blocks. The RMS value is given by:
$$ \text{RMS} = \sqrt{ \frac{1}{N} \sum_{n=0}^{N-1} x^2[n] } $$
which can be approximated by a moving average of squared samples followed by a square root using a CORDIC core. Similarly, the crest factor (peak/RMS) and kurtosis (fourth central moment) provide sensitivity to impulsive events such as bearing spalls or structural impacts. In our system, these could be computed in parallel with the FFT, as the FPGA has abundant spare resources. The table below compares the computational requirements for the three types of features.
| Feature | Mathematical Formulation | FPGA Resources (est.) | Bandwidth Saving vs. Raw |
|---|---|---|---|
| Spectral peaks (FFT-based) | Single-tone amplitudes via FFT | 4 DSP, 6 BRAM | >99% |
| RMS level | $$\sqrt{\frac{1}{N}\sum x^2}$$ | 2 DSP, 1 BRAM | >99.9% |
| Crest factor | $$ \max(|x|) / \text{RMS} $$ | 3 DSP, 1 BRAM | >99.9% |
| Kurtosis | $$ \frac{1}{N} \frac{\sum (x-\mu)^4}{\sigma^4} $$ | 5 DSP, 2 BRAM | >99.9% |
The extremely low bandwidth required for extracted features (a few bytes per second) leaves ample room for the ground control station to simultaneously monitor hundreds of parameters from multiple UAV drones. This scalability is critical for swarm operations and fleet management.
Conclusion
In this work, we have designed, implemented, and validated an FPGA-based real-time monitoring system tailored for the vibration environment of UAV drone mission payloads. The system achieves a bandwidth reduction of over two orders of magnitude by performing on-board FIR filtering and FFT analysis, transmitting only the essential spectral information to the ground control station. The hardware implementation on an Artix-7 FPGA demonstrates efficient resource usage, with the core processing pipeline occupying less than 6% of logic and 12% of block RAM. Vibration tests with a multi-tone input confirmed that the system can resolve frequency components with 1 Hz accuracy and completely suppress out-of-band interference. The integrated SD card storage ensures that raw data is preserved for comprehensive offline diagnostics. This approach provides a practical solution for enhancing the situational awareness of UAV drone operators, enabling early detection of mechanical anomalies and thus improving flight safety and mission reliability. Future work will focus on integrating additional feature extraction modules, such as envelope analysis for bearing fault detection, and adapting the system to higher-frequency vibration environments using re-configurable filter coefficients.