The increasing demand for lightweight, miniaturized, and high-performance photoelectric payloads on UAV drones has driven the development of advanced embedded controllers. In this work, we present a dual-core heterogeneous controller based on the OMAPL138 processor, integrating an ARM926EJ-S core and a TMS320C674x DSP core. The ARM core handles multi-task management and high-level command processing, while the DSP core executes real-time servo stabilization and complex control algorithms. By leveraging the SysLink inter-processor communication framework, we achieve efficient data exchange between cores using shared memory, message queues, and ring buffers. The controller extends eight-channel serial ports via the EMIF bus, adopts a combined GDB and CCS dynamic debugging method, and realizes accurate control of the photoelectric payload. Compared with traditional PowerPC+DSP architectures, our design reduces volume and power consumption, improves communication speed and reliability, and is particularly suitable for UAV drone applications.
1. Introduction
UAV drones equipped with photoelectric payloads perform critical missions such as reconnaissance, surveillance, target ranging, positioning, and tracking. The payload controller must manage multiple tasks simultaneously—handling ground station commands, switching sensor modes, and controlling servo systems for stabilization and tracking. Traditional controllers often employ separate PowerPC and DSP chips, communicating via RS-422 serial links. This approach suffers from large footprint, high power dissipation, low data rate, and susceptibility to interference. To overcome these limitations, we selected the OMAPL138 processor from Texas Instruments, which integrates an ARM9 and a C674x DSP on a single die. This architecture allows us to partition workloads optimally: the ARM runs Linux for task scheduling and peripheral management, while the DSP runs a real-time operating system (Sys/BIOS) for high-speed servo loops and sensor data fusion. The result is a compact, low-power, high-performance controller that meets the stringent requirements of modern UAV drone platforms.
2. OMAPL138 Processor Overview
The OMAPL138 device features an ARM926EJ-S core (max 456 MHz) and a TMS320C674x floating/fixed-point DSP core (max 456 MHz). It provides a rich set of peripherals including EMIFA, EMIFB, EDMA3, SPI, UART, USB, and Ethernet. The dual cores share access to the same external memory and peripherals, enabling tight coupling. Key advantages for UAV drone payload control include:
- Unified memory map allowing shared memory regions for inter-core communication.
- Advanced power management with multiple operating modes, reducing overall system power.
- High-performance DSP capable of real-time PID, Kalman filtering, and adaptive control algorithms.
- ARM core with Linux OS for network stacks, file systems, and complex device drivers.
Table 1 summarizes the core specifications relevant to our design.
| Parameter | ARM926EJ-S | TMS320C674x DSP |
|---|---|---|
| Clock Frequency | 375–456 MHz | 375–456 MHz |
| Architecture | 32-bit RISC (ARMv5TEJ) | 32-bit VLIW (C674x) |
| Floating Point | Software | Hardware (single/double) |
| L1 Cache | 16 KB I-cache + 16 KB D-cache | 32 KB L1P + 32 KB L1D |
| L2 Cache | — | 256 KB |
| OS Support | Linux, WinCE | Sys/BIOS, TI-RTOS |
3. SysLink Inter-Core Communication
The heterogeneous dual-core architecture requires a robust software framework for synchronization and data exchange. SysLink (System Link) from Texas Instruments provides both low-level IP (Inter-Processor Communication) and high-level APIs. We utilize two key SysLink components: MessageQ for variable-length message passing and RingIO for streaming data via circular buffers. The shared memory region is partitioned into three areas:
- SR0_Ipc: Used for control messages (e.g., mode commands, status reports).
- SR1: ARM→DSP data buffer (sensor commands, tracking offsets, mode flags).
- SR2: DSP→ARM data buffer (position, velocity, gyro readings, tracking results).
Memory mapping for the 128 MB DDR2 is arranged as shown in Table 2. The ARM kernel boot parameters include mem=32M@0xc0000000 mem=64M@0xc4000000 to reserve the upper 32 MB for DSP and shared use.
| Region | Address Range | Size | Owner | Purpose |
|---|---|---|---|---|
| ARM OS & Apps | 0xC0000000–0xC1FFFFFF | 32 MB | ARM | Linux kernel, user space |
| ARM Data | 0xC2000000–0xC3FFFFFF | 32 MB | ARM | Heap, stacks, temporary |
| DSP Code & Data | 0xC4000000–0xC5FFFFFF | 32 MB | DSP | Sys/BIOS, control algorithms |
| Shared Memory | 0xC6000000–0xC6FFFFFF | 16 MB | Both | MessageQ, RingIO buffers |
| Reserved | 0xC7000000–0xC7FFFFFF | 16 MB | — | Future expansion |
The communication latency using MessageQ for a single 20 KB data block is measured as approximately 80 μs. This is a dramatic improvement over the 1400 μs required by the traditional RS-422 (115200 bps) approach, as compared in Section 6.
4. Dual-Core Debugging Methodology
Developing software for heterogeneous multi-core systems can be challenging. We adopted a hybrid debugging approach combining GDB (for ARM) and Code Composer Studio (CCS, for DSP). The ARM side runs a GDB server over Ethernet, while the DSP side connects via JTAG. The static debugging interface is shown conceptually (no figure referenced). The procedure is:
- ARM loads the SysLink module and starts the DSP using the slave loader.
- PC uses CCS to load DSP debug symbols.
- ARM starts the GDB server and loads ARM symbols.
- PC connects to the GDB server and loads ARM symbols.
- Breakpoints are set on both cores; execution is controlled from the PC.
This approach allows simultaneous debugging of both cores. For example, we can halt the DSP at a control loop entry while stepping through ARM task scheduler code. The flexibility dramatically reduces development time for UAV drone payload firmware.
5. Controller Hardware and Software Design
The controller hardware is built around the OMAPL138 with the following key components:
- NAND Flash (K9F4G08U0D, 512 MB): Stores bootloader, kernel, and file system.
- DDR2 (MT47H64M16HR, 128 MB, 400 MHz): Main memory for both cores.
- Serial Expansion (TL16CP754CIPM): 8-channel RS-422 via EMIF bus for high-speed communication with sensors and ground station.
- ADC (AD7606): 16-bit, 8-channel for tachometer and gyro signals.
- RVDT Converter (AD2S80): Resolver-to-digital for position feedback.
- PWM Output: Drives motor amplifier modules.
- GPIO: Controls power to thermal imager and laser.
- Ethernet (RJ45): For GDB debugging and NFS boot.
The ARM core runs Linux 3.10 with custom drivers for the serial expander, GPIO, and SysLink. The DSP core runs Sys/BIOS 6.40 with real-time tasks for servo control. Inter-core communication follows the client-server model: ARM is the client (data manager), DSP is the server (control engine). Messages carry command IDs and parameters; bulk data (e.g., gyro readings, tracking offsets) are transferred via RingIO buffers.
5.1 Implementation of Tracking Mode
The photoelectric payload supports multiple operational modes: storage, manual, scan, track, lock, and search. The tracking mode is the most demanding in terms of real-time performance and data throughput. We describe its implementation to illustrate the dual-core cooperation. The tracking loop involves:
- ARM receives field-of-view (FOV) data from the TV/IR camera, tracking error from the tracker, and control commands from the ground station.
- ARM writes FOV, tracking offset, sensor switch flags, and drift compensation into SR1 (RingIO).
- ARM sends a message via MessageQ (ARM→DSP) to enable tracking mode.
- DSP receives the message, reads SR1 data, acquires tachometer and gyro signals, and executes the control law:
$$u_{\text{PID}}(t) = K_p e(t) + K_i \int_0^t e(\tau) d\tau + K_d \frac{d e(t)}{dt}$$
where $e(t)$ is the angular tracking error. The DSP then computes the motor control output through cascade loops: inner rate loop (gyro) and outer position loop (resolver).
- DSP writes the current position, velocity, and mode status into SR2.
- DSP sends a message via MessageQ (DSP→ARM) to notify new data ready.
- ARM reads SR2 and transmits the data to the ground station and tracker.
This cycle repeats at 1 kHz (servo loop rate). The total latency from sensor input to motor output is less than 500 μs, well within the requirement for stable tracking on a UAV drone.
6. Performance Comparison
Table 3 compares our OMAPL138-based controller to a traditional PowerPC+DSP solution. Key metrics include physical dimensions, power consumption, communication speed, and reliability.
| Metric | PowerPC + DSP (Traditional) | OMAPL138 (This Work) |
|---|---|---|
| Board Area (mm²) | 160×100 + 120×100 ≈ 28,000 | 185×130 ≈ 24,050 |
| Power Consumption (W) | 12 + 15 = 27 | 15 |
| Inter-core Communication | RS-422 (115200 bps) | Shared Memory (DDR2) |
| Transmission Time for 20 KB (μs) | 1400 | 80 |
| Electromagnetic Immunity | Low (serial cable) | High (internal bus) |
| Real-time Determinism | Moderate | High |
| Scalability (bandwidth) | Fixed | Increases with memory bus frequency |
The 17-fold reduction in transmission time (1400→80 μs) for a typical 20 KB data packet is critical for closed-loop control on a UAV drone. The lower power consumption also extends flight endurance. Furthermore, elimination of external serial cables improves reliability in vibration and EMI-prone environments.
7. Experimental Results
Field tests were conducted on a UAV drone equipped with the developed controller. The tracking accuracy (RMS) for a moving ground target at 2 km range was measured as 0.05° in azimuth and 0.08° in elevation, meeting the specification of 0.1°. The controller maintained stable operation over 4 hours of continuous flight with no communication errors. The DSP load averaged 65% at 456 MHz, leaving headroom for future algorithm upgrades.
The SysLink MessageQ latency was measured using a loopback test. The one-way transmission time for a 64-byte message (including software overhead) was 8.3 μs, while a 4 KB message took 22 μs. These values are far below the control loop period of 1 ms.
8. Conclusion
We have presented a photoelectric payload controller based on the OMAPL138 dual-core processor for UAV drone applications. By partitioning task management and servo control between the ARM and DSP cores, and utilizing SysLink for efficient shared-memory communication, we achieved a compact, low-power, high-reliability solution. The tracking mode implementation demonstrates the feasibility of real-time dual-core collaboration. Compared to traditional architectures, our design reduces board area by 14%, power by 44%, and inter-core communication latency by 94%. These improvements directly benefit UAV drone performance, enabling longer missions, better tracking accuracy, and higher resistance to environmental disturbances. Future work will explore multi-core extensions and adaptive control algorithms implemented on the DSP.